I am a Doctoral Candidate majoring in Statistics with a concentration on Statistical Learning (Machine Learning). I have had prior working experience as an Component Design Engineer in a major semiconductors MNC. I am passionate about technology and education, with strong technical skills, and experience in teaching. In my free time, I enjoy photography, paper craft, music and mountains. I would be an avid gamer, but since I lack the necessary twitch reaction needed for most games, and I stay mainly with strategy and role-playing games. I am very opinionated on religion, theology, philosophy, politics, sociology, and believe strongly in social justice and welfare of children.
| Website | https://www.nicklim.com |
|---|---|
| Address | G3.02, Department of Mathematics & Statistics, University of Waikato, 3210 Hamilton East, Hamilton, New Zealand |
I was a teaching assistant for MATH165/166 (General/Management Mathematics), STAT111/121 (Introduction to Statistical Methods/Statistics for Science. My responsibilities includes teaching first-year undergraduate students; grading assignments and tests and provide test supervision for both first-year and second-year undergraduate papers for the Mathematics and Statistics Department. I also provided 1:1 Tutorials on request from Disability Office and Pacific-Aid Scholarship Office.
Beyond my teaching duties I also worked as a Community Ambassador for the faculty during the University open days from 2015-2018 and presented mathematical concepts in an interesting manner and explain the concepts in simple to understand manner for people without mathematical background, as well as to promote the value of a qualifications in Mathematics and Statistics in someone's everyday life
I was responsible for developing the design methodology to verify the functionality. and electrical and signal compliance of custom System-on-chip designs. I worked closely with design engineers to resolve simulation issues, meet design deadlines, and automate tasks through scripts and improvement on engineering workflow, as recognition for my attentiveness to my internal customers, I was the top recipient of peer-level recognition awards within my functional group.
I also assisted the design engineers in debugging unexpected results in their simulations and in the process, I caught multiple design issues, including the $700 million dollars Cougarpoint PCH SATA recall.
Methodology Development and maintenance of transistor-level optimization for Process migration of System-on-Chip design (2007, 2009-2011)I was part of a `skunkworks'-type team, to develop the methodology and automating the translation of circuit design between process nodes, during which I developed a common framework for multi-variable, multi-objective optimization of transistor designs. For my contributions to the team, I received a division-level award for this project from the business group.
Development and maintenance of IBIS (I/O Buffer Information Specification)/.LIB models (mathematical model) generation for signal integrity noise and timing analysis. (2007-2010)I was responsible for developing an automated methodology to convert complex I/O drivers to an equivalent Thevenin or Norton circuit. Beyond the developing the automation I also close the mismatch between the complex transistor design and the `simple' mathematical models while working within the limitations of the specifications.
Graduate Intern trainer and Department Trainer(2007-2010)}I was responsible to prepare new hires to improve their understanding of the Intel design flow, knowledge in circuit design and simulations, as well as soft-skills including writing reports and up-selling themselves to the managers and their internal customers. Beyond one-on-few training, I also provided department-level training on the Basics of UNIX computing and the proprietary computing environment.
Beside usual work responsibility, I was also the functional group representative to the Office environment focus team. I've successfully lobbied for an employee clubhouse, additional parking spaces, tea time, and improvements in the office pantries as well as improved the appeal of the new office building, while minimizing impact of the move to the new building on productivity and employee morale.
University of Waikato
My research topic for my doctoral studies is on the "Ensemble Learning in High Dimension Datasets" under the supervision of Dr. Robert Durrant. I was awarded Best Conference Presenter for the New Zealand Mathematics and Statistics Postgraduate Conference 2017 for talk titled "Meeting the Modern Prometheus: An introduction to Deep Learning from a Mathematics and Statistics Perspective", I was also a recipient of the "University of Waikato, Doctoral Scholarship"
University of Waikato
My research was on The star decomposition of bipartite graphs, in the field of combinatorics. I was awarded the A Zualauf studentship for Masters students. Additionally I am also admitted into the Golden Keys Honour Society. I graduated with a First Class Honours with an overall GPA of 8.25/9.0
Multimedia University
I was a multiple entrant into the Dean's List, and the runner up of the Intervarsity Engineering Competition in my Second Year of my course. I completed my degree with a First Class Honours, and a GPA of 3.67/4.00
Lim, N. J. S., Durrant R. J. (2017). Linear Dimensionality Reduction in Linear Time: Johnson-Lindenstrauss-type Guarantees for Random Subspace, Preprint, for consideration for publication in Data-Mining and Knowledge Discovery Journal. https://arxiv.org/abs/1705.06408
Lim, J. S. (2015). Star Decompositions of Bipartite Graphs (Thesis, Master of Science (MSc)). University of Waikato, Hamilton, New Zealand. Retrieved from http://hdl.handle.net/10289/9303
SoC Design Conference (ISOCC), 2009 International System on Chip Conference, Busan, South Korea Process technologies generate increasing challenges for layout efficiency at the 65nm process. This has increased the reliance on standard cell library development in order to simultaneously meet the demand of today's tight design schedules. However due to IP-specific design constraints, customized logic cells are frequently necessary to achieve design closure. We explore a design flow that efficiently characterizes a standard cell for power, timing and reliability considerations within custom design, and further synthesizes promising circuit alternatives using a spec-driven optimization approach through transistor level sizing. This methodology provides a unique ability for determining tradeoffs between physical design and circuit design challenges.
Electronic Materials and Packaging, 2007. EMAP 2007. International Conference on Electronic Materials and Packaging, Daejon, South Korea
Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th Electronics Packaging Technology Conference, Singapore This paper presents a comprehensive core power delivery excitation modeling approach, covering from complex pre-silicon hand estimate to simple post-silicon reverse engineering. Blending the two approaches, an optimized method is recommended to provide the most appropriate method in deriving the next generation core currents for power delivery analysis.
Some of my miscellenous work.